1. Field of the Invention
Generally, the present disclosure relates to the field of manufacturing of microstructures, such as integrated circuits, and, more particularly, analysis techniques used for process monitoring and/or process control.
2. Description of the Related Art
In manufacturing microstructures, such as integrated circuits, micromechanical devices, opto-electronic components and the like, device features, such as circuit elements, are typically formed on an appropriate substrate by patterning the surface portions of one or more material layers previously formed on the substrate. Since the dimensions, i.e., the length, width and height, of individual features are steadily decreasing to enhance performance and improve cost effectiveness, these dimensions have to be maintained within tightly set tolerances in order to guarantee the required functionality of the complete device. Usually, a large number of process steps have to be carried out for completing a microstructure and, thus, the dimensions of the features during the various manufacturing stages have to be thoroughly monitored to maintain process control and to avoid further cost-intensive process steps owing to process tools that fail to meet the specifications in the various manufacturing stages.
For example, in sophisticated CMOS devices, a very large number of transistors, such as N-channel transistors and P-channel transistors, have to be formed in and above a semiconductor layer, wherein these transistor elements may comprise critical device features, such as gate electrodes and the like, which may have a critical dimension of approximately 50 nm and less in currently available products. In addition to steadily shrinking critical dimensions of the device features, new materials and process strategies may frequently have to be implemented in order to further enhance reliability, performance and cost-effectiveness. For example, the manufacturing of sophisticated field effect transistors requires new technologies due to significant limitations, which may be encountered by conventional planar transistor structures based on a gate dielectric material in the form of silicon dioxide, silicon oxynitride and other “conventional” dielectric materials, since these materials may typically result in significantly increased leakage currents, thereby resulting in undue heat generation which may not be compatible with requirements of many types of semiconductor devices. The limitations of well-established and well-approved dielectric materials in gate electrode structures have fueled new technology approaches, such as non-planar transistor configurations and/or sophisticated gate electrode structures. For instance, the scalability of planar transistor configurations may be significantly expanded by using complex gate electrode structures on the basis of high-k dielectric materials, which are to be understood as materials having a dielectric constant of 10.0 or higher, in combination with metal-containing electrode materials. Consequently, new materials, such as high-k dielectric materials and the like, may have to be implemented into the overall manufacturing flow, thereby requiring appropriate manufacturing techniques for depositing and patterning these materials. For this reason, also any new types of byproducts may be created during the processing of these materials, which may also require a thorough monitoring and investigation with respect to any interactions with other materials and manufacturing processes.
In still other approaches for enhancing transistor performance of complex integrated circuits, strain-inducing mechanisms may be implemented into the overall manufacturing flow for forming field effect transistors since a strained channel region of a silicon-based transistor may provide enhanced transistor performance due to a modified charge carrier mobility caused by the strained silicon-based material. For this purpose, strain-inducing semiconductor alloys, such as silicon/germanium, silicon/carbon and the like, may be incorporated into the active regions in a local manner, thereby selectively inducing a desired type of strain in individual transistor elements. Also in this case, sophisticated patterning and deposition techniques may be required which have to be applied within tightly set process tolerances in order to maintain overall device variability at a low level.
Similarly, after completing the circuit elements in a device level of complex integrated circuits, a contact level has to be formed, which may be considered as an interface between the circuit elements in the device level and a complex metallization system, which may be considered as a wiring fabric for connecting the individual transistor elements and other circuit elements in accordance with the required circuit function. Since at least in some device regions a very high density of individual circuit elements may have to be provided, the contact level may have to be formed on the basis of extremely complex deposition and patterning techniques in order to provide appropriate interlayer dielectric materials and patterning the same so as to form contact openings and filling the same with an appropriate metal-containing material. For example, the formation of contact openings in an interlayer dielectric material represents an extremely challenging manufacturing stage for very complex integrated circuits, which may, for instance, comprise densely packed memory areas and the like, since densely spaced contact openings with a high aspect ratio and with critical dimensions of approximately 100 nm and significantly less may have to be formed in a reliable and predictable manner. Consequently, the interaction of the different materials and processes may have a significant influence on the overall production yield in modern semiconductor facilities.
Moreover, typically, very complex metallization systems are required in modern semiconductor devices, wherein the complexity of the metallization system may reside in the fact that a plurality of metallization layers may have to be formed on top of each other, wherein complex material systems may also have to be provided in each of the metallization layers. For example, in modern integrated circuits including a very large number of circuit elements, typically, copper in combination with sophisticated dielectric materials, so-called low-k dielectric materials or ultra low-k (ULK) materials, may be used in order to reduce signal propagation delay in the metallization system. Due to copper's intrinsic characteristics, substantially not to form volatile etch byproducts on the basis of most of the well-established plasma assisted etch chemistries, typically, a process technique is applied in which a dielectric material may first be patterned so as to receive corresponding openings, such as trenches and via openings, which are subsequently filled with the copper material by electrochemical deposition techniques. However, due to the fact that copper may readily diffuse in silicon dioxide, silicon, a plurality of low-k dielectric materials and the like, a reliable confinement of the copper is required, since even minute amounts of copper diffusing to device regions such as active regions of transistors, may result in a significant change of the overall device characteristics. For this reason, complex barrier material systems may be provided, for instance, in the form of tantalum, tantalum nitride, ruthenium, titanium, titanium nitride and the like, which may provide a desired diffusion hindering effect and which may also provide the mechanical and chemical integrity of the copper material. Moreover, although copper-based interconnect structures may have a significantly low electrical resistivity compared to, for instance, aluminum, the reduced dimensions of the interconnect structures may nevertheless result in very high current densities, thereby also requiring strong interfaces between the copper material and the surrounding dielectric material that may have to be provided by the barrier material and corresponding cap materials in order to obtain the required performance with respect to electromigration. Consequently, in the complex manufacturing sequence for forming metallization layers, sensitive dielectric materials may have to be patterned based on appropriate plasma assisted etch processes, thereby also creating a plurality of etch byproducts, which may have a significant effect on the further processing of the device. Moreover, after patterning the sensitive dielectric material systems, one or more barrier materials, possibly in combination with seed materials, may have to be deposited by very sophisticated deposition techniques, wherein the process result may essentially depend on the surface conditions of the dielectric materials, corresponding defects and particles formed thereon and the like. Thereafter, the openings, such as trenches and via openings, are filled with the copper materials by very advanced electrochemical deposition techniques, which may require well-defined surface conditions of the previously deposited barrier/seed material in order to obtain the required bottom-to-top fill behavior without generating deposition-related irregularities, which may result in contact failure or reduced electrical performance. Thereafter, any excess material, such as copper in combination with barrier and seed materials, has to be removed, for instance by using polishing techniques and the like, wherein, frequently, an increased mechanical stress may be created, for instance, by a chemical mechanical polishing (CMP) process, which may result in the creation of high defect rate due to the nature of the polishing process and due to the fact that the sensitive dielectric material may typically exhibit a less mechanical stability compared to conventional dielectric materials, such as silicon dioxide and silicon nitride. For instance, in particular at the edge region of substrates, a significant material delamination may be observed, which may result in an increased degree of particle contamination of exposed surface areas of the substrate and of process tools and transport containers.
Hence, at the various stages during the fabrication of complex microstructure devices, such as integrated circuits, surface conditions, such as material characteristics, the presence of particles, their lateral size and characteristics and the like, have to be thoroughly monitored in order to maintain the process output of the various manufacturing stages within the tightly set tolerances. For this reason, a plurality of complex inspection and analysis techniques have been developed which may be applied during the various manufacturing stages. For example, frequent optical inspection techniques may be available for detecting particles, wherein, however, due to the restricted resolution of these techniques, the detection may be restricted to particles of moderately large size so that critical device areas, such as areas having a pronounced surface topography, for instance due to the presence of trenches, contact openings and the like, may not yield meaningful results since typically the lateral dimensions of these device features may be significantly smaller compared to the wavelength of the optical inspection tool. In other cases, very sensitive and efficient analysis techniques may be provided on the basis of infrared spectroscopy using an interference modulated probing beam, which after interaction with a material of interest may be efficiently converted into a spectrum by Fourier transformation that in turn may be analyzed with respect to chemical characteristics of the material of interest. Although this technique may provide fast and accurate analysis results, the spatial resolution thereof is less compared to other optical inspection techniques so that only an average characterization of the chemical characteristics may be obtained. With other sophisticated analysis techniques, such as AFM (atomic force microscopy), the size and shape of particles in the sub micrometer range may be detected by scanning a corresponding surface portion wherein, however, other characteristics, such as chemical characteristics, chemical bonds within the material of interest and the like, may be very difficult to be determined on the basis of these techniques. Similarly, electron microscopy in transmission mode (TEM) may be efficiently applied in order to determine the presence and size and shape of particles, even provided on surface areas having a very pronounced topography, for instance within contact openings and the like, wherein, however, other characteristics, such as chemical characteristics and the like may be difficult to be identified on the basis of electron microscopy. Moreover, very sophisticated sample preparation may be required which may typically necessitate the destruction of the sample of interest. Moreover, in many of these sophisticated analysis techniques, the difficulty in determining characteristics of particles of interest may stem from the fact that the local neighborhood of the particle may also have a significant influence on the measurement results so that the response of the particle of interest may be difficult to be extracted from the response of the neighboring material.
The present disclosure is directed to various methods and systems that may avoid, or at least reduce, the effects of one or more of the problems identified above.